In order to reduce a leakage current during standby of a SRAM circuit, it is effective to set the potential of a ground interconnection of a memory array at a potential higher than a ground potential (0V) (a potential between a power supply potential and the ground potential). This can reduce a sub-threshold leakage current of a MOS (Metal Oxide Semiconductor) transistor in an OFF state which forms a memory cell.
In Japanese Patent Laying-Open No. 2004-206745 (PTD 1), for example, a potential control circuit for controlling the potential of a ground interconnection is provided to thereby control the potential of the ground interconnection during standby at about 0.4V. Specifically, this potential control circuit is formed of three elements, namely, a switch for fixing the potential of the ground interconnection at a ground potential during operation, a diode-connected NMOS (N-channel MOS) transistor for determining the potential of the ground interconnection during standby, and a resistance for continuously passing a current.